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data sheet mos integrated circuit pd780306, 780308 8-bit single-chip microcontroller description pd780306 and 780308 are products in the pd780308 subseries within the 78k/0 series, which incorporates lcd controller/driver, 8-bit resolution a/d converter, timer, serial interface, interrupt functions and many other peripheral hardwares. a one-time prom product capable of operating in the same power supply voltage range as of the mask rom product, eprom product, pd78p0308, and other development tools are available. for the details of functional description, refer to the following user? manual. pd780308, 780308y subseries user? manual : u11377e 78k/0 series user? manual (instruction) : u12326e features large on-chip rom & ram minimum instruction execution time can be varied from high speed (0.4 s) to ultra-low speed (122 s) i/o ports: 57 (including segment signal output alternate-function pins) lcd controller/driver supply voltage v dd = 2.0 to 5.5 v (operable in any mode) 8-bit resolution a /d converter : 8 channels serial interface : 3 channels timer: 5 channels supply voltage : v dd = 2.0 to 5.5 v applications celullar phones, compact disk players, cameras, meters, etc. item program memory data memory product name (rom) internal high-speed ram internal extended ram lcd display ram pd780306 48k bytes 1024 bytes 1024 bytes 40 4 bits pd780308 60k bytes the mark shows major revised points. document no. u11105ej3v2ds00 (3rd edition) date published august 2005 n cp(k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
pd780306, 780308 2 data sheet u11105ej3v2ds ordering information part number package pd780306gc- -8eu 100-pin plastic lqfp (fine pitch) (14 x 14) pd780306gc- -8eu-a 100-pin plastic lqfp (fine pitch) (14 x 14) pd780306gf- -3ba 100-pin plastic qfp (14 x 20) pd780306gf- -3ba-a 100-pin plastic qfp (14 x 20) pd780308gc- -8eu 100-pin plastic lqfp (fine pitch) (14 x 14) pd780308gc- -8eu-a 100-pin plastic lqfp (fine pitch) (14 x 14) pd780308gf- -3ba 100-pin plastic qfp (14 x 20) pd780308gf- -3ba-a 100-pin plastic qfp (14 x 20) remark 1. indicates rom code suffix. 2. products that have the part numbers suffixed by ?a?are lead-free products.
pd780306, 780308 3 data sheet u11105ej3v2ds 78k/0 series lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries names. remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same. pd78054 with iebus tm controller. pd78054 with enhanced serial i/o pd78078y with enhanced serial i/o and limited function pd78054 with timer and enhanced external interface 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 pd78018f with uart and d/a converter, and enhanced i/o pd780034a pd780988 pd780034ay 64-pin pd780024a with expanded ram pd780024a with enhanced a/d converter on-chip inverter control circuit and uart. emi-noise reduced. pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series lcd drive pd78064 with enhanced sio, and expanded rom and ram emi-noise reduced version of the pd78064 basic subseries for driving lcds, on-chip uart bus interface supported pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) 42/44-pin 64-pin 64-pin pd78018f with enhanced serial i/o 80-pin 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. romless version of the pd78078 100-pin 100-pin emi-noise reduced version of the pd78078 inverter control pd780208 100-pin vfd drive pd78044f with enhanced i/o and vfd c/d. display output total: 53 pd780208 pd78098b 100-pin pd780024a pd780024ay 80-pin 80-pin pd780852 pd780824 for automobile meter driver. on-chip dcan controller 100-pin pd780958 for industrial meter control on-chip automobile meter controller/driver meter control 80-pin on-chip iebus controller 80-pin on-chip controller compliant with j1850 (class 2) pd780833y pd780948 on-chip dcan controller 64-pin pd780078 pd780078y pd780034a with timer and enhanced serial i/o pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y pd78070a pd78070ay pd78078 pd78078y pd780018ay control pd78075b pd780065 pd78044h pd780232 80-pin 80-pin for panel control. on-chip vfd c/d. display output total: 53 pd78044f with n-ch open-drain i/o. display output total: 34 pd78044f 80-pin basic subseries for driving vfd. display output total: 34 120-pin pd780308 with enhanced display function and timer. segment signal output: 40 pins max. pd780318 pd780328 120-pin 120-pin pd780308 with enhanced display function and timer. segment signal output: 32 pins max. pd780308 with enhanced display function and timer. segment signal output: 24 pins max. pd780338 on-chip dcan controller specialized for dcan controller function 80-pin pd780703y pd780702y 64-pin pd780816
pd780306, 780308 4 data sheet u11105ej3v2ds the major functional differences among the subseries are shown below. function rom timer 8-bit 10-bit 8-bit serial interface i/o external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a expansion control pd78075b 32 k to 40 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 88 1.8 v yes pd78078 48 k to 60 k pd78070a 61 2.7 v pd780058 24 k to 60 k 2 ch 3 ch (time-division uart: 1 ch) 68 1.8 v pd78058f 48 k to 60 k 3 ch (uart: 1 ch) 69 2.7 v pd78054 16 k to 60 k 2.0 v pd780065 40 k to 48 k ? ch (uart: 1 ch) 60 2.7 v pd780078 48 k to 60 k 2 ch 8 ch 3 ch (uart: 2 ch) 52 1.8 v pd780034a 8 k to 32 k 1 ch 3 ch (uart: 1 ch) 51 pd780024a 8 ch pd78014h 2 ch 53 pd78018f 8 k to 60 k pd78083 8 k to 16 k 1 ch (uart: 1 ch) 33 inverter pd780988 16 k to 60 k 3 ch note ? ch 8 ch 3 ch (uart: 2 ch) 47 4.0 v yes control vfd pd780208 32 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2.7 v drive pd780232 16 k to 24 k 3 ch 4 ch 40 4.5 v pd78044h 32 k to 48 k 2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 v pd78044f 16 k to 40 k 2 ch lcd pd780338 48 k to 60 k 3 ch 2 ch 1 ch 1 ch 10 ch 1 ch 2 ch (uart: 1 ch) 54 1.8 v drive pd780328 62 pd780318 70 pd780308 48 k to 60 k 2 ch 1 ch 8 ch 3 ch (time-division uart: 1 ch) 57 2.0 v pd78064b 32 k 2 ch (uart: 1 ch) pd78064 16 k to 32 k bus pd780948 60 k 2 ch 2 ch 1 ch 1 ch 8 ch 3 ch (uart: 1 ch) 79 4.0 v yes interface pd78098b 40 k to 60 k 1 ch 2 ch 69 2.7 v supported pd780816 32 k to 60 k 2 ch 12 ch ? ch (uart: 1 ch) 46 4.0 v meter pd780958 48 k to 60 k 4 ch 2 ch 1 ch 2 ch (uart: 1 ch) 69 2.2 v control dash pd780852 32 k to 40 k 3 ch 1 ch 1 ch 1 ch 5 ch 3 ch (uart: 1 ch) 56 4.0 v board control pd780824 32 k to 60 k 2 ch (uart: 1 ch) 59 note 16-bit timer: 2 channels 10-bit timer: 1 channel v dd min. value
pd780306, 780308 5 data sheet u11105ej3v2ds overview of function 48k bytes 60k bytes 1024 bytes 1024 bytes 40 4 bits 8 bits 32 registers (8 bits 8 registers 4 banks) on-chip minimum instruction execution time cycle modification function 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 mhz operation) 122 s (at 32.768 khz operation) 16-bit operation multiplication/division (8 bits 8 bits,16 bits 8 bits) bit manipulation (set, reset, test, boolean operation) bcd correction, etc. total : 57 cmos input : 0 2 cmos i/o : 55 8-bit resolution 8 channels segment signal output : maximum 40 common signal output : maximum 4 bias : 1/2 or 1/3 switchable ? 3-wire serial i/o/sbi/2-wire serial i/o mode selectable : 1 channel ? 3-wire serial i/o/uart mode selectable : 1 channel ? 3-wire serial i/o mode : 1 channel ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 3 (14-bit pwm output capability : 1) 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (at main system clock: 5.0 mhz operation) 32.768 khz (at subsystem clock: 32.768 khz operation) 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (at main system clock 5.0 mhz operation) internal : 13, external : 6 internal : 1 1 internal : 1, external: 1 v dd = 2.0 to 5.5 v ? 100-pin plastic lqfp (fine pitch) (14 x 14) ? 100-pin plastic qfp (14 x 20) internal memory item product name general-purpose registers minimum instruction execution time timer output clock output buzzer output test input supply voltage instruction set lcd controller/driver when main system clock selected when subsystem clock selected i/o ports (including segment signal output pins) a/d converter pd780308 timer vectored interrupt sources package serial interface maskable non-maskable software pd780306 rom high-speed ram extended ram lcd display ram
pd780306, 780308 6 data sheet u11105ej3v2ds contents 1. pin configuration (top view) .......................................................................................................... 7 2. block diagram ............................................................................................................................... ..... 10 3. pin f unc ti ons ................................................................................................................ ....................... 11 3.1 port pins ............................................................................................................................... .......................... 11 3.2 non-port pins ............................................................................................................................... ................. 13 3.3 pin i/o circuits and recommended connection of unused pins ............................................ 14 4. memory space ............................................................................................................................... ....... 18 5. peripheral hardware function feature .............................................................................. 19 5.1 port ............................................................................................................................... .................................... 19 5.2 clock generator ............................................................................................................................... ........ 20 5.3 timer/event counter ............................................................................................................................... .. 20 5.4 clock output control circuit ............................................................................................................ 23 5.5 buzzer output control circuit .......................................................................................................... 23 5.6 a/d converter ............................................................................................................................... ............... 24 5.7 serial interface ............................................................................................................................... .......... 25 5.8 lcd controller/driver ............................................................................................................................ 27 6. interrupt functions and test functions .............................................................................. 28 6.1 interrupt functions ............................................................................................................................... .. 28 6.2 test functions ............................................................................................................................... .............. 32 7. standby function .............................................................................................................................. 3 3 8. reset function ............................................................................................................................... ..... 33 9. in st ruc ti on set .............................................................................................................. ..................... 34 10. electrical specifications ............................................................................................................. 37 11. characteristic curves (reference value) ........................................................................... 58 12. package drawings ............................................................................................................................ 60 13. recommended soldering conditions ....................................................................................... 62 appendix a. development tools ......................................................................................................... 64 appendix b. related documents ........................................................................................................ 67
pd780306, 780308 7 data sheet u11105ej3v2ds 1. pin configuration (top view) ?100-pin plastic lqfp (fine pitch) (14 x 14) p11/ani1 p10/ani0 98 99 100 97 96 95 94 93 92 91 90 89 88 87 av ss p117 p116 p115 p114/rxd p113/txd p112/sck3 p111/so3 p110/si3 p05/intp5 p04/intp4 p03/intp3 p02/intp2 86 85 84 83 82 p01/intp1/ti01 p00/intp0/ti00 reset xt2 xt1/p07 v dd1 1 p12/ani2 p13/ani3 2 3 p14/ani4 4 p15/ani5 5 p16/ani6 6 p17/ani7 7 v dd0 8 av ref 9 p100 10 p101 11 v ss1 12 p102 13 p103 14 p30/to0 15 p31/to1 16 p32/to2 17 p33/ti1 18 19 20 p34/ti2 p35/pcl 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 45 s13 44 43 42 41 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 v ss0 v lc2 v lc1 v lc0 bias com3 p36/buz 21 p37 22 com0 23 24 25 com1 com2 50 s18 49 48 47 46 s17 s16 s15 s14 p27/sck0 72 73 74 75 70 71 69 68 67 66 65 64 63 62 61 60 59 58 57 56 p70/si2/r x d p26/so0/sb1 p25/si0/sb0 p80/s39 p81/s38 p82/s37 p83/s36 p84/s35 p85/s34 p86/s33 p87/s32 p90/s31 p91/s30 p92/s29 p93/s28 p94/s27 p95/s26 p96/s25 p97/s24 55 54 53 52 51 s23 s22 s21 s20 s19 80 79 78 77 76 x1 x2 ic p72/sck2/asck p71/so2/t x d 81 cautions 1. connect directly the ic (internally connected) pin to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remark when using in applications where noise from inside the microcontroller has to be reduced, it is recommended that countermeasures against the noise are taken, such as supplying power separately to v dd0 and v dd1 , and connecting v dd0 and v dd1 to ground lines separately.
pd780306, 780308 8 data sheet u11105ej3v2ds ?100-pin plastic qfp (14 x 20) cautions 1. connect directly the ic (internally connected) pin to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remark when using in applications where noise from inside the microcontroller has to be reduced, it is recommended that countermeasures against the noise are taken, such as supplying power separately to v dd0 and v dd1 , and connecting v dd0 and v dd1 to ground lines separately. p26/so0/sb1 p25/si0/sb0 98 99 100 97 96 95 94 93 92 91 90 89 88 87 p80/s39 p81/s38 p82/s37 p83/s36 p84/s35 p85/s34 p86/s33 p87/s32 p90/s31 p91/s30 p92/s29 p93/s28 p94/s27 86 85 84 83 82 p95/s26 p96/s25 p97/s24 s23 s22 s21 1 p27/sck0 p70/si2/r x d 2 3 p71/so2/t x d 4 p72/sck2/asck 5 ic 6 x2 7 x1 8 v dd1 9 xt1/p07 10 xt2 11 reset 12 p00/intp0/ti00 13 p01/intp1/ti01 14 p02/intp2 15 p03/intp3 16 p04/intp4 17 p05/intp5 18 19 p110/si3 20 p111/so3 p112/sck3 21 p113/txd 22 p114/rxd 23 24 25 p115 p116 81 26 p117 av ss 27 p10/ani0 28 p11/ani1 29 30 p12/ani2 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 50 49 48 47 46 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p103 p102 v ss1 p101 p100 av ref v dd0 p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 77 78 79 80 75 76 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 v ss0 v lc2 v lc1 v lc0 bias com3 com2 com1 com0
pd780306, 780308 9 data sheet u11105ej3v2ds ani0-ani7 : analog input asck : asynchronous serial clock av ref : analog reference voltage av ss : analog ground bias : lcd power supply bias control buz : buzzer clock com0-com3 : common output ic : internally connected intp0-intp5 : interrupt from peripherals p00-p05, p07 : port0 p10-p17 : port1 p25-p27 : port2 p30-p37 : port3 p70-p72 : port7 p80-p87 : port8 p90-p97 : port9 p100-p103 : port10 p110-p117 : port11 pcl : programmable clock reset : reset rxd : receive data s0-s39 : segment output sb0, sb1 : serial bus sck0, sck2, sck3 : serial clock si0, si2, si3 : serial input so0, so2, so3 : serial output ti00, ti01, ti1, ti2 : timer input to0-to2 : timer output txd : transmit data v dd0 , v dd1 : power supply v lc0 -v lc2 : lcd power supply v ss0 , v ss1 :g round x1, x2 : crystal (main system clock) xt1, xt2 : crystal (subsystem clock)
pd780306, 780308 10 data sheet u11105ej3v2ds 2. block diagram remark the internal rom capacity varies depending on the product. to0/p30 16-bit timer/ event counter ti00/intp0/p00 ti01/intp1/p01 to1/p31 8-bit timer/ event counter 1 ti1/p33 to2/p32 8-bit timer/ event counter 2 ti2/p34 watchdog timer watch timer si0/sb0/p25 serial interface 0 so0/sb1/p26 sck0/p27 si3/p110 serial interface 3 so3/p111 sck3/p112 a/d converter av ss av ref ani0/p10- ani7/p17 interrupt control intp0/p00- intp5/p05 buzzer output buz/p36 clock output control pcl/p35 p00 port 0 p01-p05 p07 port 1 p10-p17 port 11 p110-p117 port 2 p25-p27 port 3 p30-p37 port 7 p70-p72 port 8 p80-p87 port 9 p90-p97 port 10 p100-p103 lcd controller/ driver s0-s23 bias f lcd reset x1 x2 xt1/p07 xt2 78k/0 cpu core rom ram system control v dd0 , v dd1 v ss0 , v ss1 ic s24/p97- s31/p90 s32/p87- s39/p80 com0-com3 v lc0 -v lc2 so2/txd/p71 serial interface 2 rxd/p114 sck2/asck/p72 si2/rxd/p70 txd/p113
pd780306, 780308 11 data sheet u11105ej3v2ds 3. pin functions 3.1 port pins (1/2) alternate function pin name i/o input only port 1 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. note 2 input p25 p26 p27 p30 p31 p32 p33 p34 p35 p36 p37 port 7 3-bit input/output port. input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. p00 p01 p02 p03 p04 p05 p07 note 1 p10-p17 input input only input intp0/ti00 intp1/ti01 intp2 intp3 intp4 intp5 xt1 ani0-ani7 input p70 p71 p72 input input input input input port 3 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. input/ output input/ output port 2 3-bit input/output port. input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. input/ output input/ output input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. port 0 7-bit input/output port. input/ output notes 1. when using the p07/xt1 pins as an input port, set (1) bit 6 (frc) of the processor clock control register (pcc) (the on-chip feedback resistor of the subsystem clock oscillator should not be used). 2. when using the p10/ani0 to p17/ani7 pins as the a/d converter analog input, port 1 is set to input mode. however, internal pull-up resistor is not automatically used. so0/sb1 si0/sb0 sck0 function on reset to0 to1 to2 ti1 ti2 pcl buz si2/rxd so2/txd sck2/asck
pd780306, 780308 12 data sheet u11105ej3v2ds 3.1 non-port pins (2/2) alternate function pin name i/o port 8 8-bit input/output port input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. input/output port/segment signal output function can be specified in 2-bit unit by the lcd display control register (lcdc). port 9 8-bit input/output port input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. input/output port/segment signal output function can be specified in 2-bit unit by the lcd display control register (lcdc). p80-p87 input/ output input s39-s32 s31-s24 input input/ output p90-p97 input/ output p100-p103 input input function on reset port 10 4-bit input/output port input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. led direct drive capability. p110 p111 p112 p113 p114 p115-p117 port 11 8-bit input/output port input/output can be specified bit-wise. when used as an input port, internal pull-up resistor can be used by software. falling edge detection capability. input/ output si3 so3 sck3 txd rxd
pd780306, 780308 13 data sheet u11105ej3v2ds 3.2 non-port pins (1/2) intp0 intp1 intp2 intp3 intp4 intp5 si0 si2 si3 so0 so2 so3 sb0 sb1 sck0 sck2 sck3 rxd txd asck ti00 ti01 ti1 ti2 to0 to1 to2 pcl buz s0-s23 s24-s31 s32-s39 com0-com3 v lc0 -v lc2 bias alternate function pin name i/o function on reset input output output output output input serial interface serial clock input/output. serial interface serial data input/output. input output input input/ output input/ output output serial interface serial data output. input serial interface serial data input. input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. input input input input input input input input input input input output input p00/ti00 p01/ti01 p02 p03 p04 p05 p25/sb0 p70/rxd p110 p26/sb1 p71/txd p111 p25/si0 p26/so0 p27 p72/asck p112 p70/si2, p114 p71/so2, p113 p72/sck2 p00/intp0 p01/intp1 p33 p34 p30 p31 p32 p35 p36 p97-p90 p87-p80 output output asynchronous serial interface serial data input. asynchronous serial interface serial data output. asynchronous serial interface serial clock input. external count clock input to 16-bit timer (tm0). capture trigger signal input to capture register (cr00). external count clock input to 8-bit timer (tm1). external count clock input to 8-bit timer (tm2). 16-bit timer (tm0) output (shared with 14-bit pwm output). 8-bit timer (tm1) output. 8-bit timer (tm2) output. clock output (for main system clock, subsystem clock trimming). buzzer output. lcd controller/driver segment signal output. lcd controller/driver common signal output. lcd drive voltage. split resistors can be incorporated by mask option. lcd drive power supply.
pd780306, 780308 14 data sheet u11105ej3v2ds 3.2 non-port pins (2/2) a/d converter analog input. reference voltage input of a/d converter (shared with analog power supply). ground potential of a/d converter. set the same potential as v ss0 . system reset input. main system clock oscillation crystal connection. subsystem clock oscillation crystal connection. positive power supply for port block. ground potential for port block. positive power supply (except port and analog block). ground potential (except port and analog block). internally connected. connect directly to v ss0 or v ss1 pin. pin name i/o ani0-ani7 av ref av ss reset x1 x2 xt1 xt2 v dd0 v ss0 v dd1 v ss1 ic function on reset alternate function p10-p17 p07 input input input input input input input 3.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the input/output circuit configuration of each type, refer to figure 3-1 . table 3-1. input/output circuit type of each pin (1/2) p00/intp0/ti00 p01/intp1/ti01 p02/intp2 p03/intp3 p04/intp4 p05/intp5 p07/xt1 p10/ani0-p17/ani7 p25/si0/sb0 p26/so0/sb1 p27/sck0 p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 connect to v ss0 . connect to v dd0 . input input/output input input/output 2 8-c 16 11-b 10-b 5-h 8-c pin name i/o recommended connection when not used input/output circuit type independently connect to v ss0 through resistor. independently connect to v dd0 or v ss0 through resistor.
pd780306, 780308 15 data sheet u11105ej3v2ds i/o recommended connection when not used pin name input/output circuit type 5-h 8-c 5-h 8-c 17-c 5-h 8-c 17-b 18-a 2 16 table 3-1. input/output circuit type of each pin (2/2) p35/pcl p36/buz p37 p70/si2/rxd p71/so2/txd p72/sck2/asck p80/s39 to p87/s32 p90/s31 to p97/s24 p100 to p103 p110/si3 p111/so3 p112/sck3 p113/txd p114/rxd p115 to p117 s0 to s23 com0 to c0m3 v lc0 to v lc2 bias reset xt2 av ref av ss ic independently connect to v dd0 through resistor. input/output output input leave unconnected. leave unconnected. connect to v ss0 . connect to v ss0 . connect directly to v ss0 or v ss1 . independently connect to v dd0 or v ss0 through resistor.
pd780306, 780308 16 data sheet u11105ej3v2ds pull-up enable data output disable input enable p-ch in/out v dd0 v dd0 p-ch n-ch v ss0 in type 2 type 5-h type 8-c type 11-b type 16 type 10-b schmitt-triggered input with hysteresis characteristic figure 3-1. pin input/output circuits (1/2) pull-up enable data output disable p-ch in/out v dd0 v dd0 p-ch n-ch v ss0 pull-up enable data output disable p-ch in/out v dd0 v dd0 p-ch n-ch open-drain v ss0 pull-up enable data output disable input enable p-ch in/out v dd0 v dd0 p-ch n-ch n-ch v ref + p-ch (threshold voltage) comparator v ss0 v ss0 feedback cut-off p-ch xt1 xt2
pd780306, 780308 17 data sheet u11105ej3v2ds p-ch n-ch p-ch n-ch p-ch n-ch v lc0 v lc1 v lc2 com data n-ch p-ch out v ss1 figure 3-1. pin input/output circuits (2/2) type 17-b type 18-a type 17-c out p-ch n-ch p-ch n-ch p-ch n-ch v lc0 v lc1 v lc2 seg data v ss1 pull-up enable data output disable input enable p-ch in/out v dd0 v dd0 p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch v lc0 v lc1 v lc2 seg data v ss0 v ss1
pd780306, 780308 18 data sheet u11105ej3v2ds pd780306 bfffh pd780308 efffh 4. memory space the memory map of pd780306 and 780308 is shown in figure 4-1. figure 4-1. memory map note the capacity of internal rom differs according to product. (refer to the following table.) last address of internal rom nnnnh product name ffffh ff00h feffh fedfh fa80h fa7fh fa58h fa57h nnnnh+1 nnnnh 0000h nnnnh 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h reserved internal extended ram 1024 8 bits program area callf entry area program area callt table area vector table area general-purpose registers 32 8 bits internal high-speed ram 1024 8 bits lcd display ram 40 4 bits program memory space data memory space special function register (sfr) 256 8 bits 1000h internal rom note fee0h f800h f7ffh reserved f400h f3ffh reserved fb00h faffh
pd780306, 780308 19 data sheet u11105ej3v2ds 5. peripheral hardware function feature 5.1 port there are two kinds of i/o port. cmos input (p00, p07) : 2 cmos input/output (p01 to p05, port 1 to 3, 7 to 11) : 55 total : 57 table 5-1. functions of ports function name pin name dedicated input port input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used by software. input/output port. input/output specifialbe bit-wise. when used as input port, on-chip pull-up resistor can be used by software. input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used by software. input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used by software. input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used by software. input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used by software. input/output port/segment signal output function specifiable in 2-bit units by lcd display control register (lcdc). input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used by software. input/output port/segment signal output function specifiable in 2-bit units by lcd display control register (lcdc). input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used by software. direct led drive capability. input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used by software. test input flag (krif) is set to 1 by falling edge detection. port 0 port 1 port 2 port 3 port 7 port 8 port 9 port 10 port 11 p00, p07 p01 to p05 p10 to p17 p25 to p27 p30 to p37 p70 to p72 p80 to p87 p90 to p97 p100 to p103 p110 to p117
20 pd780306, 780308 data sheet u11105ej3v2ds interval timer 1 channel 2 channels 1 channel 1 channel external event counter 1 channel 2 channels timer output 1 output 2 outputs pwm output 1 output pulse width measurement 2 inputs square wave output 1 output 2 outputs one-shot pulse output 1 output interrupt request 2 2 1 1 test input 1 input 5.2 clock generator there are two kinds of clocks, main system clock and subsystem clock. the minimum instruction execution time can also be changed. 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (main system clock: in 5.0 mhz operation) 122 s (subsystem clock: in 32.768 khz operation) figure 5-1. clock generator block diagram 5.3 timer/event counter five timer/event counter channels are incorporated. 16-bit timer/event counter : 1 channel 8-bit timer/event counter : 2 channels watch timer : 1 channel watchdog timer : 1 channel table 5-2. operation of timer/event counter 16-bit timer/ event counter 8-bit timer/ event counter watch timer watchdog timer operating mode function x1 x2 xt1/p07 xt2 f xt f xx 2 f xx 2 2 f xx 2 3 f xx 2 4 f xt 2 f x 2 stop f x cpu clock (f cpu ) subsystem clock oscillator main system clock oscillator frequency divider selec- tor prescaler prescaler standby control circuit selec- tor watch timer clock output function clock to peripheral hardware to intp0 sampling clock f xx 1/2
pd780306, 780308 21 data sheet u11105ej3v2ds figure 5-2. 16-bit timer/event counter block diagram inttm1 to2/p32 inttm2 to1/p31 f xx /2-f xx /2 9 fx x /2 11 ti1/p33 ti2/p34 f xx /2-f xx /2 9 fx x /2 11 internal bus 8-bit compare register (cr10) match match selec- tor 8-bit timer register 1 (tm1) clear selec- tor selector 8-bit compare register (cr20) 8-bit timer register 2 (tm2) clear selec- tor output control circuit output control circuit internal bus selec- tor figure 5-3. 8-bit timer/event counter block diagram ti01/p01/intp1 watch timer output ti00/p00/intp0 2f xx f xx f xx /2 f xx /2 2 intp0 inttm01 intp1 inttm00 to0/p30 internal bus selec- tor 16-bit capture/compare register (cr00) match match pwm pulse output control circuit output control circuit edge detector 16-bit timer register (tm0) clear 16-bit capture/compare register (cr01) internal bus selec- tor selector
22 pd780306, 780308 data sheet u11105ej3v2ds figure 5-4. watch timer block diagram figure 5-5. watchdog timer block diagram f xx 2 6 f xx 2 7 f xx 2 8 f xx 2 9 f xx 2 11 f xx 2 5 f xx 2 4 f xx 2 3 reset intwdt non-maskable interrupt request intwdt maskable interrupt request prescaler selector 8-bit counter control circuit f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 f xx /2 7 f xt f w f w 2 14 f w 2 13 intwt inttm3 selec- tor prescaler 5-bit counter selector selector selector to 16-bit timer/event counter to lcd controller/driver
pd780306, 780308 23 data sheet u11105ej3v2ds 5.4 clock output control circuit clocks of the following frequency can be output as clock outputs. 19.5 khz/39.1khz/78.1 khz/156 khz/313 khz/625 khz/1.25 mhz/2.5 mhz/5.0 mhz (main system clock: in 5.0 mhz operation) 32.768 khz (subsystem clock: in 32.768 khz operation) figure 5-6. clock output control circuit block diagram 5.5 buzzer output control circuit clocks of the following frequency can be output as buzzer outputs. 1.2 khz/2.4 khz/4.9 khz/9.8 khz (main system clock : in 5.0 mhz operation) figure 5-7. buzzer output control circuit block diagram pcl/p35 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xt selector synchronization circuit f xx /2 f xx output control circuit buz/p36 selector f xx /2 9 f xx /2 10 f xx /2 11 output control circuit
24 pd780306, 780308 data sheet u11105ej3v2ds ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 av ref av ss intad intp3 selec- tor sample & hold circuit intp3/p03 voltage comparator series resistor string tap selec- tor successive approximation register (sar) control circuit edge detector a/d conversion result register (adcr) internal bus 5.6 a/d converter eight 8-bit resolution a/d converter channels are incorporated. the following two types of start-up method are available. hardware start software start figure 5-8. a/d converter block diagram
pd780306, 780308 25 data sheet u11105ej3v2ds figure 5-9. serial interface channel 0 block diagram 5.7 serial interface three clocked serial interface channels are incorporated. serial interface channel 0 serial interface channel 2 serial interface channel 3 table 5-3. serial interface channel block diagram 3-wire serial i/o mode (msb/lsb-first switchable) (msb/lsb-first switchable) (msb/lsb-first switchable) sbi (serial bus interface) mode (msb-first) 2-wire serial i/o mode (msb-first) asynchronous serial interface (with dedicated baud rate (uart) mode generator, data i/o pin switch function) function serial interface channel 0 serial interface channel 2 serial interface channel 3 si0/sb0/p25 so0/sb1/p26 sck0/p27 intcsi0 to2 f xx /2-f xx /2 8 internal bus selector selector serial i/o shift register 0 (sio0) output latch busy/acknowledge output circuit bus release/command/ acknowledge detector serial clock counter interrupt request signal generator serial clock control circuit selector
26 pd780306, 780308 data sheet u11105ej3v2ds figure 5-11. serial interface channel 3 block diagram si3/p110 so3/p111 sck3/p112 intcsi3 f xx /2-f xx /2 8 internal bus serial i/o shift register 3 (sio3) serial clock counter interrupt request signal generator serial clock control circuit selector figure 5-10. serial interface channel 2 block diagram r x d/si2/p70 t x d/so2/p71 asck/sck2/p72 intser intsr/intcsi2 f xx -f xx /2 10 intst receive buffer register (rxb/sio2) direction control circuit receive shift register (rxs) direction control circuit transmit shift register (txs/sio2) transmit control circuit receive control circuit sck output control circuit baud rate generator internal bus selector selector r x d/p114 t x d/p113
pd780306, 780308 27 data sheet u11105ej3v2ds 5.8 lcd controller/driver an lcd controller/driver with the following functions is incorporated. selection of 5 types of display mode 16 of the segment signal of outputs can be switched to input/output ports in units of 2. (p80/s39 to p87/s32, p90/s31 to p97/s24) table 5-4. display mode types and maximum number of display pixels bias method time division common signal used maximum number of display pixels static com0 (com1 to com3) 40 (40 segments 1 common) 2 com0, com1 80 (40 segments 2 commons) 3 com0 to com2 3 com0 to com2 4 com0 to com3 160 (40 segments 4 commons) 1/2 1/3 120 (40 segments 3 commons) figure 5-12. lcd controller/driver block diagram v lc2 v lc1 v lc0 bias com3 com2 com1 com0 s39/p80 s0 s23 s24/p97 lcdcl f w 2 9 f w 2 8 f w 2 7 f w 2 6 internal bus display data memory segment data selector port output data segment driver prescaler selector timing controller lcd drive voltage generator common driver lcd drive mode switch circuit
28 pd780306, 780308 data sheet u11105ej3v2ds 6. interrupt functions and test functions 6.1 interrupt functions there are twenty-one of interrupt sources of three different kinds, as shown below. non-maskable : 1 maskable : 19 software : 1
pd780306, 780308 29 data sheet u11105ej3v2ds table 6-1. interrupt source list interrupt source name interrupt type default priority note 1 internal/ external vector table address basic configuration type note 2 watchdog timer overflow (with watchdog timer mode 1 selected) watchdog timer overflow (with interval timer mode selected) pin input edge detection serial interface channel 0 transfer termination serial interface channel 2 uart reception error generation serial interface channel 2 uart reception termination serial interface channel 2 3-wire transfer termination serial interface channel 2 uart transmission termination reference time interval signal from watch timer 16-bit timer register and capture/compare register (cr00) match signal generation 16-bit timer register and capture/compare register (cr01) match signal generation 8-bit timer/event counter 1 match signal generation 8-bit timer/event counter 2 match signal generation a/d converter conversion termination serial interface channel 3 transfer termination brk instruction execution intwdt intwdt intp0 intp1 intp2 intp3 intp4 intp5 intcsi0 intser intsr intcsi2 intst inttm3 inttm00 inttm01 inttm1 inttm2 intad intcsi3 brk trigger (a) (b) internal 0004h 0006h 0008h 000ah 000ch 000eh 0010h 0014h 0018h 001ah 001ch 001eh 0020h 0022h 0024h 0026h 0028h 002ah 003eh (c) (d) external 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 maskable non- maskable (e) software internal (b) notes 1. default priority is a priority order when more than one maskable interrupt request is generated simultaneously. 0 is the highest and 17 the lowest. 2. basic configuration types (a) to (e) correspond to those shown on the next page.
30 pd780306, 780308 data sheet u11105ej3v2ds interrupt request standby release signal internal bus vector table address generator priority control circuit figure 6-1. basic configuration of interrupt functions (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt mk ie pr isp if interrupt request internal bus priority control circuit vector table address generator standby release signal (c) external maskable interrupt (intp0) sampling clock select register (scs) if ie pr isp external interrupt mode register (intm0) sampling clock edge detector interrupt request internal bus mk priority control circuit vector table address generator standby release signal
pd780306, 780308 31 data sheet u11105ej3v2ds figure 6-1. basic configuration of interrupt functions (2/2) (d) external maskable interrupt (except intp0) (e) software interrupt internal bus interrupt request vector table address generator priority control circuit if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specification flag if internal bus interrupt request edge detector vector table address generator standby release signal external interrupt mode register (intm0, intm1) mk ie pr isp priority control circuit
32 pd780306, 780308 data sheet u11105ej3v2ds 6.2 test functions there are two test functions as shown in table 6-2. table 6-2. test input source list figure 6-2. basic configuration of test function if : test input flag mk : test mask flag test input source name trigger internal/external intwt watch timer overflow internal intpt11 port 11 falling edge detection external mk if internal bus standby release signal test input signal
pd780306, 780308 33 data sheet u11105ej3v2ds 7. standby function the standby function is a function to reduce the current consumption and there are the following two kinds of standby functions. halt mode : halts cpu operating clock and can reduce average current consumption by the intermittent operation along with the normal operation. stop mode : halts main system clock oscillation. halts all operations with the main system clock and sets ultra- low current consumption state with subsystem clock only. figure 7-1. standby function note halting the main system clock enables the current consumption to be reduced. when the cpu is operated by the subsystem clock, the main system clock should be halted by setting the bit 7 (mcc) of the processor clock control register (pcc). the stop instruction is not available. caution when the main system clock is stopped and the system is operated by the subsystem clock, the main system clock should be returned to after securing the oscillation stabilization time by a program. 8. reset function there are the following two kinds of resetting methods. external reset by reset pin. ? internal reset by watchdog timer hung-up time detection. css=1 css=0 main system clock operation interrupt request stop mode main system clock oscillation halted stop instruction () interrupt request halt instruction halt mode clock supply to cpu halted, oscillation maintained () subsystem clock operation note halt instruction interrupt request halt mode note clock supply to cpu halted, oscillation maintained ()
34 pd780306, 780308 data sheet u11105ej3v2ds 9. instruction set (1) 8-bit instruction mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz #byte a r note sfr saddr !addr16 psw [de] [hl] $addr16 1 none 2nd operand 1st operand add addc sub subc and or xor cmp mov mov mov add addc sub subc and or xor cmp mov mov add addc sub subc and or xor cmp mov mov mov mov mov mov mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp [hl+byte] [hl+b] [hl+c] ror rol rorc rolc inc dec inc dec push pop ror4 rol4 mulu divuw dbnz dbnz a r b, c sfr saddr !addr16 psw [de] [hl] [hl+byte] [hl+b] [hl+c] x c note except r = a
pd780306, 780308 35 data sheet u11105ej3v2ds (2) 16-bit instruction movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand 1st operand #word ax rp note sfrp saddrp !addr16 sp none ax rp sfrp saddrp !addr16 sp addw subw cmpw movw movw movw movw movw note movw movw movw movw movw movw movw movw incw, decw push, pop movw xchw note only when rp = bc, de, hl (3) bit manipulation instruction mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr 2nd operand 1st operand a.bit sfr.bit saddr.bit psw.bits [hl].bit cy $addr16 none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 mov1 mov1 mov1 mov1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 not1 bt bf btclr bt bf btclr bt bf btclr bt bf btclr bt bf btclr mov1 and1 or1 xor1
36 pd780306, 780308 data sheet u11105ej3v2ds (4) call instruction/branch instruction call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz callt callf call br br basic instruction compound instruction br, bc, bnc, bz, bnz 2nd operand 1st operand ax !addr16 !addr11 [addr5] $addr16 (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop bt, bf, btclr dbnz
37 pd780306, 780308 data sheet u11105ej3v2ds 10. electrical specifications absolute maximum ratings (t a = 25 c) v dd av ref av ss v i v o v an i oh i ol parameter symbol test conditions rating unit v v v v v v v ma ma ma ma ma ma ma ma ma ma c c supply voltage input voltage output voltage analog input voltage output current, high p10-p17 analog input pin 1 pin total for p01-p05, p10-p17, p25-p27, p70-p72, p110-p117 total for p30-p37, p80-p87, p90-p97, p100-p103 ?.3 to +7.0 ?.3 to v dd + 0.3 ?.3 to +0.3 ?.3 to v dd + 0.3 ?.3 to v dd + 0.3 av ss ?0.3 to av ref + 0.3 ?0 ?5 ?5 30 15 note 60 40 note 140 100 note 50 20 note ?0 to +85 ?5 to +150 peak value r.m.s. value peak value r.m.s. value peak value r.m.s. value peak value r.m.s. value 1 pin total for p01-p05, p10-p17, p110-p117 total for p30-p37, p100-p103 total for p25-p27, p70-p72, p80-p87, p90-p97 operating ambient temperature storage temperature t a t stg note the r.m.s. value should be calculated as follows: [r.m.s. value] = [peak value] duty caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. capacitance (t a = 25 c, v dd = v ss = 0 v) output current, low input capacitance output capacitance i/o capacitance pf pf pf parameter symbol test conditions min. typ. max. unit 15 15 15 c in c out c io f = 1 mhz unmeasured pins returned to 0 v.
38 pd780306, 780308 data sheet u11105ej3v2ds x1 x2 ic c1 c2 r1 x1 x2 ic c1 c2 r1 main system clock oscillator characteristics (t a = ?0 to +85 c, v dd = 2.0 note 4 to 5.5 v) unit mhz ms mhz ms mhz ns max. 5 4 5 10 30 5.0 500 recommended circuit parameter oscillator frequency (f x ) note 1 oscillation stabilization time note 2 oscillator frequency (f x ) note 1 oscillation stabilization time note 2 x1 input frequency (f x ) note 1 x1 input high/low level width (t xh , t xl ) min. 1 1 1.0 85 resonator ceramic resonator crystal resonator external clock notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. 3. after v dd reaches the minimum oscillator voltage range. 4. actually, oscillation start voltage or over, and v dd = 2.0 or over (for an external clock, v dd = 2.0 or over is ok). cautions 1. when using the main system clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. wiring should be as short as possible. wiring should not cross other signal lines. wiring should not be placed close to a varying high current. the potential of the oscillator capacitor ground should be the same as v ss1 . do not ground it to the ground pattern in which a high current flows. do not fetch a signal from the oscillator. 2. if the main system clock oscillator is operated by the subsystem clock when the main system clock is stopped, reswitching to the main system clock should be performed after the stable oscillation time has been obtained by the program. typ. pd74hcu04 test conditions v dd = oscillator voltage range after v dd reaches oscil- lator voltage range min. v dd = oscillator voltage range v dd = 4.5 to 5.5 v note 3 note 3 x1 x2
39 pd780306, 780308 data sheet u11105ej3v2ds xt1 xt2 subsystem clock oscillator characteristics (t a = ?0 to +85 c, v dd = 2.0 note 4 to 5.5 v) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd has reached the minimum oscillation voltage range. 3. after v dd reaches the minimum oscillator voltage range. 4. actually, oscillation start voltage or over, and v dd = 2.0 or over (for an external clock, v dd = 2.0 or over is ok). cautions 1. when using the subsystem clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. wiring should be as short as possible. wiring should not cross other signal lines. wiring should not be placed close to a varying high current. the potential of the oscillator capacitor ground should be the same as v ss1 . do not ground it to the ground pattern in which a high current flows. do not fetch a signal from the oscillator. 2. the subsystem clock oscillator is designed as a low amplification circuit to provide low consump- tion current, causing misoperation to noise more frequently than the main system clock oscillator. special care should therefore be taken to wiring method when the subsystem clock is used. v dd = 4.5 to 5.5 v note 3 note 3 crystal resonator external clock oscillator frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth /t xtl ) 35 2 10 100 15 32.768 1.2 32 32 5 khz s khz s resonator recommended circuit parameter test conditions min. typ. max. unit v dd = oscillator voltage range r2 xt2 xt1 ic c4 c3
40 pd780306, 780308 data sheet u11105ej3v2ds main system clock: ceramic resonator (t a = ?0 to +85 c) manufacturer product name frequency recommended circuit constant oscillator voltage range (mhz) c1 (pf) c2 (pf) r1 (k ? ) min. (v) max. (v) matsushita efoec2004a5 2.00 built-in built-in 4.7 2.0 5.5 electronics efoec3584a4 3.58 built-in built-in 0 2.0 5.5 components efoec4194a4 4.19 built-in built-in 0 2.0 5.5 co., ltd. efoec4914a4 4.91 built-in built-in 0 2.0 5.5 efoec5004a4 5.00 built-in built-in 0 2.0 5.5 tdk corp. ccr1000k2 1.00 150 150 0 2.0 5.5 ccr3.58mc3 3.58 built-in built-in 0 2.0 5.5 ccr4.19mc3 4.19 built-in built-in 0 2.0 5.5 ccr4.91mc3 4.91 built-in built-in 0 2.0 5.5 ccr5.0mc3 5.00 built-in built-in 0 2.0 5.5 murata mfg. csb1000j 1.00 100 100 2.2 2.0 5.5 co., ltd. csa2.00mg040 2.00 100 100 0 2.0 5.5 cst2.00mg040 2.00 built-in built-in 0 2.0 5.5 csa3.58mg 3.58 30 30 0 2.0 5.5 cst3.58mgw 3.58 built-in built-in 0 2.0 5.5 csa4.19mg 4.19 30 30 0 2.0 5.5 cst4.19mgw 4.19 built-in built-in 0 2.0 5.5 csa4.91mg 4.91 30 30 0 2.0 5.5 cst4.91mgw 4.91 built-in built-in 0 2.0 5.5 csa5.00mg 5.00 30 30 0 2.0 5.5 cst5.00mgw 5.00 built-in built-in 0 2.0 5.5 caution the oscillator constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. if the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency in the application circuit. for this, it is necessary to directly contact the manufacturer of the resonator being used. recommended oscillator constant
41 pd780306, 780308 data sheet u11105ej3v2ds dc characteristics (t a = ?0 to +85 c, v dd = 2.0 to 5.5 v) 0.7 v dd v dd v 0.8 v dd v dd v 0.8 v dd v dd v 0.85 v dd v dd v v dd ?.5 v dd v v dd ?.2 v dd v 0.8 v dd v dd v 0.9 v dd v dd v 0.9 v dd v dd v 0 0.3 v dd v 0 0.2 v dd v 0 0.2 v dd v 0 0.15 v dd v 0 0.4 v 0 0.2 v 0 0.2 v dd v 0 0.1 v dd v 0 0.1 v dd v v dd ?.0 v dd v v dd ?.5 v dd v 0.6 2.0 v 0.4 v 0.2 v dd v 0.5 v parameter symbol test conditions min. typ. max. unit v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v 4.5 v dd 5.5 v 2.7 v dd < 4.5 v 2.0 v dd < 2.7 v note v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v 4.5 v dd 5.5 v 2.7 v dd < 4.5 v 2.0 v dd < 2.7 v note input voltage, low v ih1 v ih2 v ih3 v ih4 v il1 v il2 v il3 v il4 v oh v ol1 v ol2 v ol3 output voltage, high output voltage, low note when used as p07, the inverse phase of p07 should be input to xt2 using an inverter. remark unless specified otherwise, the characteristics of alternate-function pins are the same as the those of port pins. p10-p17, p30-p32, p35-p37, p80-p87, p90-p97, p100-p103 p00-p05, p25-p27, p33, p34, p70-p72, p110-p117, reset x1, x2 xt1/p07, xt2 p10-p17, p30-p32, p35-p37, p80-p87, p90-p97, p100-p103 p00-p05, p25-p27, p33, p34, p70-p72, p110-p117, reset x1, x2 xt1/p07, xt2 v dd = 4.5 to 5.5 v i oh = ? ma i oh = ?00 a p100-p103 p01-p05, p10-p17, p25-p27, p30-p37, p70-p72, p80-p87, p90-p97, p110-p117 sb0, sb1, sck0 i ol = 400 a input voltage, high v dd = 4.5 to 5.5 v, i ol = 15 ma v dd = 4.5 to 5.5 v, i ol = 1.6 ma v dd = 4.5 to 5.5 v, open-drain, pulled up (r = 1 k ? )
42 pd780306, 780308 data sheet u11105ej3v2ds symbol test conditions min. typ. max. unit p00-p05, p10-p17, p25-p27, p30-p37, p70-p72, p80-p87, p90-p97, p100-p103, 3 a p110-p117 i lih2 x1, x2, xt1/p07, xt2 20 a p00-p05, p10-p17, p25-p27, i lil1 p30-p37, p70-p72, p80-p87, p90-p97, p100-p103, ? a p110-p117 i lih2 x1, x2, xt1/p07, xt2 ?0 a i loh v out = v dd 3 a i lol v out = 0 v ? a r v in = 0 v v dd = 5.0 v 10% note 5 412ma v dd = 3.0 v 10% note 6 0.6 1.8 ma v dd = 2.2 v 10% note 6 0.35 1.05 ma v dd = 5.0 v 10% note 5 6.5 19.5 ma v dd = 3.0 v 10% note 6 0.8 2.4 ma v dd = 5.0 v 10% 1.4 4.2 ma v dd = 3.0 v 10% 500 1500 a v dd = 2.2 v 10% 280 840 a v dd = 5.0 v 10% 1.6 4.8 ma v dd = 3.0 v 10% 650 1950 a v dd = 5.0 v 10% 60 120 a v dd = 3.0 v 10% 32 64 a v dd = 2.2 v 10% 24 48 a v dd = 5.0 v 10% 25 55 a v dd = 3.0 v 10% 5 15 a v dd = 2.2 v 10% 2.5 12.5 a v dd = 5.0 v 10% 1 30 a v dd = 3.0 v 10% 0.5 10 a v dd = 2.2 v 10% 0.3 10 a v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a v dd = 2.2 v 10% 0.05 10 a dc characteristics (t a = ?0 to +85 c, v dd = 2.0 to 5.5 v) parameter v in = v dd v in = 0 v i lih1 15 45 90 k ? 5.00 mhz, crystal oscillation (f xx = 2.5 mhz) note 2 halt mode 5.00 mhz, crystal oscillation (f xx = 2.5 mhz) note 2 operating mode 5.00 mhz, crystal oscillation (f xx = 5.0 mhz) note 3 operating mode i dd1 5.00 mhz, crystal oscillation (f xx = 5.0 mhz) note 3 halt mode 32.768 khz, crystal oscillation operating mode note 4 32.768 khz, crystal oscillation halt mode note 4 i dd3 i dd2 i dd4 i dd6 i dd5 xt1 = v dd stop mode when feedback resistor is connected xt1 = v dd stop mode when feedback resistor is disconnected notes 1. current flowing v dd pin. not including a/d converter, ports, on-chip pull-up resistors or lcd dividing resistors. 2. main system clock f xx = f x /2 operation (when oscillation mode selection register (osms) is set to 00h) 3. main system clock f xx = f x operation (when osms is set to 01h) 4. when the main system clock is stopped. 5. high-speed mode operation (when processor clock control register (pcc) is set to 00h) 6. low-speed mode operation (when pcc is set to 04h) remark unless specified otherwise, the characteristics of alternate-function pins are the same as the those of port pins. input leakage current, high input leakage current, low output leakage current, high output leakage current, low software pull-up resistor supply current note 1 p01-p05, p10-p17, p25- p27, p30-p37, p70-p72, p80-p87, p90-p97, p100-p103, p110-p117
43 pd780306, 780308 data sheet u11105ej3v2ds symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.5 v dd v lcd dividing resistor r lcd 60 100 150 k ? lcd output voltage deviation note (common) lcd output voltage deviation note (segment) lcd controller/driver characteristics (at normal operation) symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.0 v dd v lcd dividing resistor r lcd 60 100 150 k ? lcd output voltage deviation note (common) lcd output voltage deviation note (segment) (1) static display mode (t a = ?0 to +85 c, v dd = 2.0 to 5.5 v) v odc i o = 5 a0 0.2 v v ods i o = 1 a0 0.2 v v lcd0 = v lcd note the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). (2) 1/3 bias method (t a = ?0 to +85 c, v dd = 2.5 to 5.5 v) note the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.7 v dd v lcd dividing resistor r lcd 60 100 150 k ? lcd output voltage deviation note (common) lcd output voltage deviation note (segment) (3) 1/2 bias method (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) note the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). v odc i o = 5 a0 0.2 v v ods i o = 1 a0 0.2 v v lcd0 = v lcd v lcd1 = v lcd 2/3 v lcd2 = v lcd 1/3 v ods i o = 1 a0 0.2 v v odc i o = 5 a0 0.2 v parameter parameter parameter v lcd0 = v lcd v lcd1 = v lcd 1/2 v lcd2 = v lcd1
44 pd780306, 780308 data sheet u11105ej3v2ds symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.0 v dd v lcd dividing resistor r lcd 60 100 150 k ? lcd output voltage v odc i o = 5 a0 0.2 v deviation note (common) lcd output voltage v ods i o = 1 a0 0.2 v deviation note (segment) lcd controller/driver characteristics (at low-voltage operation) symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.0 v dd v lcd dividing resistor r lcd 60 100 150 k ? lcd output voltage v odc i o = 5 a0 0.2 v deviation note (common) lcd output voltage v ods i o = 1 a0 0.2 v deviation note (segment) (1) static display mode (t a = ?0 to +85 c, 2.0 v v dd < 3.4 v) v lcd0 = v lcd note the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). (2) 1/3 bias method (t a = ?0 to +85 c, 2.0 v v dd < 3.4 v) note the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.0 v dd v lcd dividing resistor r lcd 60 100 150 k ? lcd output voltage v odc i o = 5 a0 0.2 v deviation note (common) lcd output voltage v ods i o = 1 a0 0.2 v deviation note (segment) (3) 1/2 bias method (t a = ?0 to +85 c, 2.0 v v dd < 3.4 v) note the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). v lcd0 = v lcd v lcd1 = v lcd 2/3 v lcd2 = v lcd 1/3 parameter parameter parameter v lcd0 = v lcd v lcd1 = v lcd 1/2 v lcd2 = v lcd1
45 pd780306, 780308 data sheet u11105ej3v2ds ac characteristics (1) basic operation (t a = ?0 to +85 c, v dd = 2.0 to 5.5 v) parameter notes 1. main system clock f xx = f x /2 operation (when oscillation mode selection register (osms) is set to 00h) 2. main system clock f xx = f x operation (when osms is set to 01h) 3. this is the value when the external clock is used. the value is 114 s (min.) when the crystal resonator is used. 4. in combination with bits 0 (scs0) and 1 (scs1) of sampling clock select register (scs), selection of f sam is possible between f xx /2 n , f xx /32, f xx /64 and f xx /128 (when n = 0 to 4). cycle time (min. instruction execution time) ti1, ti2 input frequency reset low level width ti00 input high/ low-level width ti01 input high/ low-level width ti1, ti2 input high/low-level width interrupt request input high/low- level width symbol test conditions min. typ. max. unit t cy operating on main system clock v dd = 2.7 to 5.5 v 0.8 64 s (f xx = 2.5 mhz) note 1 2.0 64 s operating on main system clock 3.5 v dd 5.5 v 0.4 32 s (f xx = 5.0 mhz) note 2 2.7 v dd < 3.5 v 0.8 32 s operating on subsystem clock 40 note 3 122 125 s f ti00 f ti00 = t tih00 + t til00 0 1/t ti00 mhz t tih00 , 3.5 v v dd 5.5 v 2/f sam +0.1 note 4 s t til00 2.7 v v dd < 3.5 v 2/f sam +0.2 note 4 s 2.0 v v dd < 2.7 v 2/f sam +0.5 note 4 s f ti01 v dd = 2.7 to 5.5 v 0 100 khz 050 khz t tih01 ,v dd = 2.7 to 5.5 v 10 s t til01 20 s f ti1 v dd = 4.5 to 5.5 v 0 4 mhz 0 275 khz t tih, v dd = 4.5 to 5.5 v 100 ns t til 1.8 s t inth , intp0 3.5 v v dd 5.5 v 2/f sam +0.1 note 4 s t inth , 2.7 v v dd < 3.5 v 2/f sam +0.2 note 4 s t inth , 2.0 v v dd < 2.7 v 2/f sam +0.5 note 4 s t intl intp1-intp5, p110-p117 v dd = 2.7 to 5.5 v 10 s 20 s t rst v dd = 2.7 to 5.5 v 10 s 20 s ti01 input frequency ti00 input frequency
46 pd780306, 780308 data sheet u11105ej3v2ds t cy vs v dd (at main system clock f xx = f x /2 operation) t cy vs v dd (at main system clock f xx = f x operation) 60 10 2.0 1.0 1 023456 0.8 0.4 60 10 2.0 1.0 1 023456 0.8 0.4 supply voltage v dd [v] cycle time t cy [ s] guaranteed operation range supply voltage v dd [v] cycle time t cy [ s] guaranteed operation range 32 2.7 3.5
47 pd780306, 780308 data sheet u11105ej3v2ds (2) serial interface (t a = ?0 to +85 c, v dd = 2.0 to 5.5 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0... internal clock output) parameter symbol test conditions min. typ. max. unit 4.5 v v dd 5.5 v 800 ns t kcy1 2.7 v v dd < 4.5 v 1600 ns 3200 ns t kh1 ,v dd = 4.5 to 5.5 v t kcy1 /2?0 ns t kl1 t kcy1 /2?00 ns 4.5 v v dd 5.5 v 100 ns t sik1 2.7 v v dd < 4.5 v 150 ns 300 ns t ksi1 400 ns t kso1 c = 100 pf note 300 ns note c is the load capacitance of sck0, so0 output line. sck0 cycle time sck0 high/low-level width si0 setup time (to sck0 ) si0 hold time (from sck0 ) so0 output delay time from sck0 t kh2 , t kl2 note c is the load capacitance of so0 output line. parameter symbol test conditions min. typ. max. unit 4.5 v v dd 5.5 v 800 ns t kcy2 2.7 v v dd < 4.5 v 1600 ns 3200 ns 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns 1600 ns t sik2 100 ns t ksi2 400 ns t kso2 c = 100 pf note 300 ns 1000 ns t r2 , t f2 sck0 cycle time sck0 high/low-level width si0 setup time (to sck0 ) si0 hold time (from sck0 ) so0 output delay time from sck0 sck0 rise, fall time (ii) 3-wire serial i/o mode (sck0...external clock input)
48 pd780306, 780308 data sheet u11105ej3v2ds (iii) sbi mode (sck0...internal clock output) parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 5.5 v 800 ns 3200 ns v dd = 4.5 to 5.5 v t kcy3 /2?0 ns t kcy3 /2?50 ns v dd = 4.5 to 5.5 v 100 ns 300 ns r = 1 k ? , v dd = 4.5 to 5.5 v 0 250 ns c = 100 pf note 0 1000 ns t kcy3 ns t kcy3 ns t kcy3 ns t kcy3 ns t kcy3 t kh3 , t kl3 t sik3 t ksi3 t kso3 t ksb t sbk t sbh t sbl t kcy3 /2 ns note r and c are the load resistance and load capacitance of the sck0, sb0 and sb1 output line. sck0 cycle time sck0 high/low-level width sb0, sb1 setup time (to sck0 ) sb0, sb1 hold time (from sck0 ) sb0, sb1 output delay time from sck0 sb0, sb1 from sck0 sck0 from sb0, sb1 sb0, sb1 high-level width sb0, sb1 low-level width (iv) sbi mode (sck0...external clock input) parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 5.5 v 800 ns 3200 ns v dd = 4.5 to 5.5 v 400 ns 1600 ns v dd = 4.5 to 5.5 v 100 ns 300 ns r = 1 k ? , v dd = 4.5 to 5.5 v 0 300 ns c = 100 pf note 0 1000 ns t kcy4 ns t kcy4 ns t kcy4 ns t kcy4 ns 1000 ns t kcy4 /2 ns note r and c are the load resistance and load capacitance of the sb0 and sb1 output line. t kcy4 t kh4 , t kl4 t sik4 t ksi4 t kso4 t ksb t sbk t sbh t sbl t r4 , t f4 sck0 cycle time sck0 high/low-level width sb0, sb1 setup time (to sck0 ) sb0, sb1 hold time (from sck0 ) sb0, sb1 output delay time from sck0 sb0, sb1 from sck0 sck0 from sb0, sb1 sb0, sb1 high-level width sb0, sb1 low-level width sck0 rise, fall time
49 pd780306, 780308 data sheet u11105ej3v2ds (v) 2-wire serial i/o mode (sck0... internal clock output) parameter symbol test conditions min. typ. max. unit v dd = 2.7 to 5.5 v 1600 ns 3200 ns v dd = 2.7 to 5.5 v t kcy5 /2?60 ns t kcy5 /2?90 ns v dd = 4.5 to 5.5 v t kcy5 /2?0 ns t kcy5 /2?00 ns 4.5 v v dd 5.5 v 300 ns 2.7 v v dd < 4.5 v 350 ns 400 ns 600 ns 300 ns r = 1 k ? , c = 100 pf note note r and c are the load resistance and load capacitance of the sck0, sb0 and sb1 output line. t kcy5 t ksi5 t kso5 t sik5 t kh5 t kl5 sck0 cycle time sck0 high-level width sck0 low-level width sb0, sb1 setup time (to sck0 ) sb0, sb1 hold time (from sck0 ) sb0, sb1 output delay time from sck0 (vi) 2-wire serial i/o mode (sck0... external clock input) note r and c are the load resistance and load capacitance of the sb0 and sb1 output line. parameter symbol test conditions min. typ. max. unit v dd = 2.7 to 5.5 v 1600 ns 3200 ns v dd = 2.7 to 5.5 v 650 ns 1300 ns v dd = 2.7 to 5.5 v 800 ns 1600 ns 100 ns t kcy6 /2 ns r = 1 k ? ,v dd = 4.5 to 5.5 v 0 300 ns c = 100 pf note 0 500 ns 1000 ns t kcy6 t kh6 t kl6 t sik6 t ksi6 t kso6 sck0 cycle time sck0 high-level width sck0 low-level width sb0, sb1 setup time (to sck0 ) sb0, sb1 hold time (from sck0 ) sb0, sb1 output delay time from sck0 sck0 rise, fall time t r6 , t f6
50 pd780306, 780308 data sheet u11105ej3v2ds (b) serial interface channel 2 (i) 3-wire serial i/o mode (sck2... internal clock output) parameter symbol test conditions min. typ. max. unit 4.5 v v dd 5.5 v 800 ns t kcy7 2.7 v v dd < 4.5 v 1600 ns 3200 ns t kh7 ,v dd = 4.5 to 5.5 v t kcy7 /2?0 ns t kl7 t kcy7 /2?00 ns 4.5 v v dd 5.5 v 100 ns t sik7 2.7 v v dd < 4.5 v 150 ns 300 ns t ksi7 400 ns t kso1 c = 100 pf note 300 ns note c is the load capacitance of sck2, so2 output line. sck2 cycle time sck2 high/low-level width si2 setup time (to sck2 ) si2 hold time (from sck2 ) so2 output delay time from sck2 note c is the load capacitance of so2 output line. parameter symbol test conditions min. typ. max. unit 4.5 v v dd 5.5 v 800 ns t kcy8 2.7 v v dd < 4.5 v 1600 ns 3200 ns 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns 1600 ns t sik8 100 ns t ksi8 400 ns t kso8 c = 100 pf note 300 ns 1000 ns t r8 , t f8 sck2 cycle time sck2 high/low-level width si2 setup time (to sck2 ) si2 hold time (from sck2 ) so2 output delay time from sck2 sck2 rise, fall time t kh8 , t kl8 (ii) 3-wire serial i/o mode (sck2...external clock input)
51 pd780306, 780308 data sheet u11105ej3v2ds asck cycle time asck high/low-level width transfer rate asck rise, fall time parameter symbol test conditions min. typ. max. unit 4.5 v v dd 5.5 v 800 ns t kcy9 2.7 v v dd < 4.5 v 1600 ns 3200 ns 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns 1600 ns 4.5 v v dd 5.5 v 39063 bps 2.7 v v dd < 4.5 v 19531 bps 9766 bps 1000 ns parameter symbol test conditions min. typ. max. unit 4.5 v v dd 5.5 v 78125 bps 2.7 v v dd < 4.5 v 39063 bps 19531 bps transfer rate (iii) uart mode (dedicated baud rate generator output) (iv) uart mode (external clock input) t kh9 , t kl9 t r9 , t f9
52 pd780306, 780308 data sheet u11105ej3v2ds (c) serial interface channel 3 (i) 3-wire serial i/o mode (sck3... internal clock output) parameter symbol test conditions min. typ. max. unit 4.5 v v dd 5.5 v 800 ns t kcy10 2.7 v v dd < 4.5 v 1600 ns 3200 ns t kh10 ,v dd = 4.5 to 5.5 v t kcy10 /2?0 ns t kl10 t kcy10 /2?00 ns 4.5 v v dd 5.5 v 100 ns t sik10 2.7 v v dd < 4.5 v 150 ns 300 ns t ksi10 400 ns t kso10 c = 100 pf note 300 ns note c is the load capacitance of sck3, so3 output line. sck3 cycle time sck3 high/low-level width si3 setup time (to sck3 ) si3 hold time (from sck3 ) so3 output delay time from sck3 note c is the load capacitance of so3 output line. parameter symbol test conditions min. typ. max. unit 4.5 v v dd 5.5 v 800 ns t kcy11 2.7 v v dd < 4.5 v 1600 ns 3200 ns 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns 1600 ns t sik11 100 ns t ksi11 400 ns t kso11 c = 100 pf note 300 ns 1000 ns t r11 , t f11 sck3 cycle time sck3 high/low-level width si3 setup time (to sck3 ) si3 hold time (from sck3 ) so3 output delay time from sck3 sck3 rise, fall time (ii) 3-wire serial i/o mode (sck3...external clock input) t kh11 , t kl11
53 pd780306, 780308 data sheet u11105ej3v2ds t til1 t tih1 1/f ti1 ti1, ti2 ti00, ti01 t til00 , t til01 t tih00 , t tih01 1/f ti00, 01 t xl t xh 1/f x v ih3 (min.) v il3 (max.) t xtl t xth 1/f xt v ih4 (min.) v il4 (max.) x1 input xt1 input 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points ac timing test point (excluding x1, xt1 input) clock timing ti timing
54 pd780306, 780308 data sheet u11105ej3v2ds t kcym t klm t khm sck0, sck2, sck3 si0, si2, si3 so0, so2, so3 t sikm t ksim t ksom input data output data t rn t fn m = 1, 2, 7, 8, 10, 11 n = 2, 8, 11 t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t ksb t sbk t ksi3.4 t kso3, 4 sb0, sb1 t r4 t f4 t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t sbl t sbh t ksb t sbk t ksi3, 4 t kso3, 4 sb0, sb1 t r4 t f4 serial transfer timing 3-wire serial i/o mode: sbi mode (bus release signal transfer): sbi mode (command signal transfer):
55 pd780306, 780308 data sheet u11105ej3v2ds asck t kcy9 t kl9 t kh9 t r9 t f9 2-wire serial i/o mode: uart mode: a/d converter characteristics (t a = ?0 to +85 c, v dd = 2.0 to 5.5 v, av ss = v ss = 0 v) parameter symbol test conditions min. typ. max. unit 888bit 2.7 v av ref 5.5 0.6 % 2.0 v av ref < 2.7 v 1.4 % t conv 19.1 200 s t samp 12/f xx s v ian av ss av ref v av ref 2.0 av dd v r ref when not operating a/d conversion 4 14 k ? ai ref when operating a/d conversion note 2 2.5 5.0 ma when not operating a/d conversion note 3 0.5 1.5 ma resolution overall error note 1 conversion time sampling time analog input voltage reference voltage av ref -av ss resistance av ref current notes 1. quantization error ( 1/2 lsb) is not included. this is expressed in proportion to the full-scale value. 2. indicates current flowing to av ref pin when the cs bit of the a/d converter mode register (adm) is 1. 3. indicates current flowing to av ref pin when the cs bit of the adm is 0. t kso5, 6 t sik5, 6 t kcy5.6 t kl5, 6 t kh5, 6 sck0 t ksi5, 6 sb0, sb1 t r6 t f6
56 pd780306, 780308 data sheet u11105ej3v2ds t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr t srel t wait v dd reset stop mode data retention mode internal reset operation halt mode operating mode v dddr stop instruction execution data retention supply voltage data retention v dddr = 1.6 v power supply current i dddr subsystem clock stop and feed-back 0.1 10 a resistor disconnected release signal set time t srel 0 s oscillation release by reset 2 17 /f x ms stabilization wait time t wait release by interrupt note ms data memory stop mode low supply voltage data retention characteristics (t a = ?0 to +85 c) parameter symbol test conditions min. typ. max. unit v dddr 1.6 5.5 v note in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time select register (osts), selection of 2 12 /f xx and 2 14 /f xx to 2 17 /f xx is possible. data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal)
57 pd780306, 780308 data sheet u11105ej3v2ds t rsl reset t intl t inth intp0?ntp5 interrupt request input timing reset input timing
58 pd780306, 780308 data sheet u11105ej3v2ds 10.0 pcc = 30h halt (x1 oscillation, xt1 oscillation) pcc = 04h pcc = 03h pcc = 02h pcc = 01h (t a = 25 ?) i dd vs v dd (f x = f xx = 5.0 mhz) 5.0 1.0 0.5 0.1 supply current i dd (ma) supply voltage v dd (v) 02345678 0.05 0.01 0.005 0.001 pcc = 00h 11. characteristic curves (reference value)
59 pd780306, 780308 data sheet u11105ej3v2ds 10.0 pcc = 30h halt (x1 oscillation, xt1 oscillation) halt (x1 stopped, xt1 oscillation) pcc = 04h pcc = 03h pcc = 02h pcc = 01h (t a = 25 ?) 5.0 1.0 0.5 0.1 supply current i dd (ma) supply voltage v dd (v) i dd vs v dd (f x = 5.0 mhz, f xx = 2.5 mhz) 02345678 0.05 0.01 0.005 0.001 pcc = 00h pcc = b0h
60 pd780306, 780308 data sheet u11105ej3v2ds 12. package drawings remark dimensions and materials of es products are the same as those of the mass production product. 100-pin plastic lqfp (fine pitch) (14x14) note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.00 0.20 14.00 0.20 0.50 (t.p.) 1.00 j 16.00 0.20 k c 14.00 0.20 i 0.08 1.00 0.20 l 0.50 0.20 f 1.00 n p q 0.08 1.40 0.05 0.10 0.05 s100gc-50-8eu, 8ea-2 s 1.60 max. h 0.22 + 0.05 ? 0.04 m 0.17 + 0.03 ? 0.07 r3 + 7 ? 3 1 25 26 50 100 76 75 51 s s n j detail of lead end c d a b r k m l p i s q g f m h
61 pd780306, 780308 data sheet u11105ej3v2ds remark dimensions and materials of es products are the same as those of the mass production product. 80 81 50 100 1 31 30 51 100-pin plastic qfp (14x20) hi j detail of lead end m q r k m l p s s n g f note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 23.6 0.4 20.0 0.2 0.30 0.10 0.6 h 17.6 0.4 i c 14.0 0.2 0.15 j 0.65 (t.p.) k 1.8 0.2 l 0.8 0.2 f 0.8 p100gf-65-3ba1-4 n p q 0.10 2.7 0.1 0.1 0.1 r5 5 s 3.0 max. m 0.15 + 0.10 ? 0.05 c d a b s
62 pd780306, 780308 data sheet u11105ej3v2ds 13. recommended soldering conditions the pd780306 and 780308 should be soldered and mounted under the conditions recommended in the table below. for soldering methods and conditions other than those recommended below, contact our sales personnel. or technical information, see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) table 13-1. surface mounting type soldering conditions (1/2) (1) pd780306gf- -3ba: 100-pin plastic qfp (14 x 20) pd780308gf- -3ba: 100-pin plastic qfp (14 x 20) soldering method soldering conditions recommended soldering symbols infrared reflow package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), ir35-00-3 number of times: three times max. vps package peak temperature: 215 c, duration: 40 sec. (at 200 c or above), vp15-00-3 number of times: three times max. wave soldering solder bath temperature: 260 c max., duration: 10 sec. max., number of times: ws60-00-1 once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 350 c max., duration: 3 sec. max. (per device side) (2) pd780306gc- -8eu: 100-pin plastic lqfp (fine pitch)(14 x 14) pd780308gc- -8eu: 100-pin plastic lqfp (fine pitch)(14 x 14) soldering method soldering conditions recommended soldering symbols infrared reflow package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), ir35-00-2 number of times: twice max. vps package peak temperature: 215 c, duration: 40 sec. (at 200 c or above), vp15-00-2 number of times: twice max. partial heating pin temperature: 350 c max., duration: 3 sec. max. (per device side) caution use of more than one soldering method should be avoided (except in the case of partial heating).
63 pd780306, 780308 data sheet u11105ej3v2ds table 13-1. surface mounting type soldering conditions (2/2) (3) pd780306gf- -3ba-a: 100-pin plastic qfp (14 x 20) pd780308gf- -3ba-a: 100-pin plastic qfp (14 x 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), ir60-207-3 count: three times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) wave soldering for details, contact an nec electronics sales representative. partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) (4) pd780306gc- -8eu-a: 100-pin plastic lqfp (fine pitch)(14 x 14) pd780308gc- -8eu-a: 100-pin plastic lqfp (fine pitch)(14 x 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), ir60-207-3 count: three times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). remark products that have the part numbers suffixed by ?a?are lead-free products.
64 pd780306, 780308 data sheet u11105ej3v2ds appendix a. development tools the following development tools are available for system development using pd780306/780308. also refer to (5) notes on using development tools . (1) language processing software ra78k0 78k/0 series common assembler package cc78k0 78k/0 series common c compiler package df780308 pd780308 subseries device file (part number : s df78064) cc78k0-l 78k/0 series common c compiler library source file (2) prom writing tools pg-1500 prom programmer pa-78p0308gc-8eu pa-78p0308gf programmer adapters connected to pg-1500 pa-78p0308kl-t pg-1500 controller pg-1500 control program (3) debugging tools ? when in-circuit emulator ie-78k0-ns is used ie-78k0-ns in-circuit emulator common to 78k/0 series ie-70000-mc-ps-b power supply unit for ie-78k0-ns ie-78k0-ns-pa performance board to enhance/expand functions of ie-78k0-ns ie-70000-98-if-c adapter when using pc-9800 series as host machine (excluding notebook type pcs) (c bus supported) ie-70000-cd-if-a pc card and interface cable when using notebook type pc as host machine (pcmcia socket supported) ie-70000-pc-if-c adapter when using ibm pc/at tm compatible as host machine (isa bus supported) ie-70000-pci-if-a interface adapter required when using pc with on-chip pci bus as host machine ie-780308-ns-em1 emulation board to emulate pd780308 subseries np-100gc emulation probe for 100-pin plastic lqfp (gc-3eu type) np-100gf emulation probe for 100-pin plastic qfp (gf-3ba type) tgc-100sdw conversion adapter to connect np-100gc and a target system board made to be mounted on 100-pin plastic lqfp (gc-8eu type) ev-9200gf-100 socket to be mounted on a target system board made for 100-pin plastic qfp (gf-3ba type) id78k0-ns integrated debugger for ie-78k0-ns sm78k0 78k/0 series common system simulator df780308 pd780308 subseries device file (part number: s df78064)
65 pd780306, 780308 data sheet u11105ej3v2ds ? when in-circuit emulator ie-78001-r-a is used ie-78001-r-a in-circuit emulator common to 78k/0 series ie-70000-98-if-c adapter required when pc-9800 series (except notebook type) is used as host machine (c bus supported) ie-70000-pc-if-c adapter required when ibm pc/at compatible machine is used as host machine (isa bus supported) ie-70000-pci-if-a interface adapter required when using pc with on-chip pci bus as host machine ie-78000-r-sv3 interface adapter and cable required when ews is used as host machine ie-780308-ns-em1 emulation board to emulate pd780308 subseries ie-780308-r-em ie-78k0-r-ex1 emulation probe conversion board necessary when using ie-780308-ns-em1 on ie-78001-r-a np-100gc emulation probe for 100-pin plastic lqfp (gc-8eu type) np-100gf emulation probe for 100-pin plastic qfp (gf-3ba type) tgc-100sdw conversion adapter to connect np-100gc and a target system board made to be mounted on 100-pin plastic lqfp (gc-8eu type) ev-9200gf-100 socket mounted on board of target system created for 100-pin plastic qfp (gf-3ba type) id78k0 integrated debugger for ie-78001-r-a sm78k0 system simulator common to 78k/0 series df780308 device file for pd780308 subseries (part number: s df78064) (4) real-time os rx78k0 78k/0 series real-time os mx78k0 78k/0 series os
66 pd780306, 780308 data sheet u11105ej3v2ds (5) notes on using development tools the package name of df780308 is the df78064. use id78k0-ns, id78k0, and sm78k0 in combination with df780308. use cc78k0 and rx78k0 in combination with ra78k0 and df780308. np-100gc and np-100gf are products of naito densei machida mfg. co., ltd. (tel (044) 822-3813). tgc-100sdw is a product of tokyo eletech corporation. contact: daimaru kogyo ltd. tokyo electronics department (tel: +81-3-3820-7112) osaka electronics department (tel: +81-6-6244-6672) for third party development tools, see the single-chip microcontroller development tool selection guide (u11069e) . the host machines and os suitable for each each software are as follows. host machine pc ews [os] pc-9800 series [japanese windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at compatible machines sparcstation tm [sunos tm , solaris tm ] software [japanese/english windows] ra78k0 note cc78k0 note pg-1500 controller note id78k0-ns id78k0 ? sm78k0 rx78k0 note mx78k0 note note this software is based on dos.
67 pd780306, 780308 data sheet u11105ej3v2ds document name document no. ra78k0 assembler package operation u14445e language u14446e structured assembly language u11789e cc78k0 c compiler operation u14297e language u14298e pg-1500 prom programmer u11940e pg-1500 controller pc-9800 series (ms-dos tm ) based eeu-1291 pg-1500 controller ibm pc series (pc dos tm ) based u10540e ie-78k0-ns u13731e ie-78k0-ns-a u14889e ie-78001-r-a planned ie-780308-ns-em1 u13304e ie-780308-r-em u11362e ep-78064 eeu-1469 sm78k0s, sm78k0 system simulator operation u14611e ver.2.10 or later windows based sm78k series system simulator external part user open u15006e ver. 2.10 or later interface specifications id78k0-ns integrated debugger o peration u14379e ver 2.00 or later windows based id78k0 integrated debugger windows based reference u11539e guide u11649e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. document name document no. pd780308, 780308y subseries user? manual u11377e pd780306, 780308 data sheet this document pd780306y, 780308y data sheet u12251e pd78p0308 data sheet u11776e pd78p0308y data sheet u11832e 78k/0 series user? manual (instruction) u12326e 78k/0 series application note basic (iii) u10182e appendix b. related documents documents related to devices documents related to development tools (user? manual) the related documents indicated in this publication may include preliminary versions. however, preliminary versions are nor marked as such.
68 pd780306, 780308 data sheet u11105ej3v2ds documents related to embedded software (user? manuals) document name document no. 78k/0 series real-time os fundamentals u11537e installation u11536e 78k/0 series os mx78k0 fundamental u12257e other documents document name document no. semiconductor selection guide-products & packages x13769e semiconductor device mounting technology manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e note see the ?emiconductor device mount manual? website (http://www.necel.com/pkg/en/mount/index.html). caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
69 pd780306, 780308 data sheet u11105ej3v2ds 1 2 3 4 voltage application waveform at input pin w aveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
70 pd780306, 780308 data sheet u11105ej3v2ds fip and iebus are trademarks of nec electronics corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at and pc dos are trademarks of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos and solaris are trademarks of sun microsystems, inc.
71 pd780306, 780308 data sheet u11105ej3v2ds regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j05.6 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 v?lizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-265 40 10 ? tyskland filial taeby, sweden tel: 08-63 87 200 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
pd780306, 780308 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of august, 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec e lectronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. " standard": " special": " specific":

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